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In-memory processing
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101	Making the Fast Case Common and the Uncommon Case Simple in Unbounded Transactional Memory E Christopher Lewis ∗ Milo M. K. Martin Add to Reading List Source URL: www.cis.upenn.edu Language: English - Date: 2007-04-14 13:06:54 Computer hardware Computer architecture Computer memory Central processing unit Cache coherency Software transactional memory Transactional memory CPU cache Cache Computing Transaction processing Concurrency control
102	Toward Predictable Performance in Software Packet-Processing Platforms Mihai Dobrescu EPFL, Switzerland Katerina Argyraki Add to Reading List Source URL: www.eecs.berkeley.edu Language: English - Date: 2012-11-24 04:26:29 Microprocessors CPU cache Central processing unit Computer memory Electronics Multi-core processor Packet Processing Xeon Transmission Control Protocol Computing Computer hardware Cache
103	Architectural Support for Parallel Reductions in Scalable Shared-Memory Multiprocessors Add to Reading List Source URL: research.ac.upc.edu Language: English - Date: 2002-03-20 08:48:05 Parallel computing CPU cache Cache Computer memory Speedup Automatic parallelization Computing Central processing unit Computer hardware
104	Appears in the Proceedings of the 35th Annual International Symposium on Computer Architecture Counting Dependence Predictors Franziska Roesner Doug Burger Add to Reading List Source URL: www.franziroesner.com Language: English - Date: 2009-10-21 14:03:38 Memory dependence prediction Memory disambiguation Branch predictor CPU cache Alpha 21264 Microarchitecture Structural load Central processing unit Explicit Data Graph Execution Computer architecture Computer engineering Computer hardware
105	MECHANISMS FOR UNBOUNDED, CONFLICT-ROBUST HARDWARE TRANSACTIONAL MEMORY Colin Blundell A DISSERTATION in Computer and Information Science Add to Reading List Source URL: www.cis.upenn.edu Language: English - Date: 2010-09-28 10:25:27 Computing Computer memory Data Transactional memory Software transactional memory Linearizability CPU cache Parallel computing Cache Transaction processing Concurrency control Data management
106	A Trace-Driven Analysis of Name and Attribute Caching in a Distributed System Ken W. Shirriff John K. Ousterhout Computer Science Division Electrical Engineering and Computer Sciences Add to Reading List Source URL: www.stanford.edu Language: English - Date: 2009-09-07 02:00:53 Memory management Central processing unit Computer memory CPU cache Lookup table Sprite Cache algorithms Database caching Computing Cache Computer hardware
107	Performance Considerations for the use of Linux in Embedded Systems 7. Juni 2004 Legal Notice Dieser Beitrag ist lizensiert unter der GNU Free Documentation License. Zusammenfassung Add to Reading List Source URL: www.free-it.org Language: English - Date: 2005-03-10 13:07:42 Central processing unit Computer memory Embedded systems Cache CPU cache Memory management unit Kernel Operating system Ring Computer architecture Computing Computer hardware
108	DATA SHEET GRIDGAIN IN-MEMORY DATA FABRIC THE FIRST ENTERPRISE-GRADE, CLOUD-SCALE DATA ACCESS ™ AND PROCESSING SOLUTION POWERED BY Add to Reading List Source URL: www.gridgain.com Language: English - Date: 2015-05-14 14:22:11 Data management Cloud computing Cloud infrastructure Apache Hadoop Database theory NoSQL In-memory database Database Apache Incubator Computing Centralized computing Database management systems
109	Application of LSTM Neural Networks in Language Modelling Daniel Soutner and Ludˇek M¨uller University of West Bohemia, Faculty of Applied Sciences, Department of Cybernetics, Univerzitn´ı 22, Plzeˇn, Czech rep. www Add to Reading List Source URL: www.kky.zcu.cz Language: English Statistics Statistical natural language processing Computational neuroscience Computational linguistics Long short term memory Computational statistics Recurrent neural network Sepp Hochreiter Artificial neural network Neural networks Science Machine learning
110	This is the author’s version of the work. The definitive work was published in Proceedings of the SPIE: Medical Imaging 2011: Image Processing, Lake Buena Vista, Orlando, FL, USA, February 12-17, 2011. Detector Defect Add to Reading List Source URL: www12.informatik.uni-erlangen.de Language: English - Date: 2011-01-15 11:56:21 Video cards Nvidia Parallel computing GPGPU CUDA Thread Nvidia Quadro Memory barrier Multi-core processor Computing Concurrent computing Computer hardware

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